The present invention relates in general to semiconductor devices for use in integrated circuits (ICs). More specifically, the present invention relates to improved fabrication methodologies and resulting structures for semiconductor device configurations (e.g., fin-type field effect transistors (FinFETs)) in which an oxide-isolated strained channel fin on a bulk substrate is provided.
Transistors are fundamental device elements of modern digital processors and memory devices. A transistor type that has emerged within the metal-oxide-semiconductor field-effect transistor (MOSFET) family of transistors, and which shows promise for scaling to ultra-high density and nanometer-scale channel lengths, is a so-called FinFET device. FinFETs are non-planar, three-dimensional (3D) devices that include a fin-shaped channel with a gate formed along the sidewalls and top surface of the channel. The use of silicon germanium in semiconductor devices such as FinFETs provides desirable device characteristics, including the introduction of strain at the interface between the silicon germanium of the active device and the underlying silicon substrate.
FinFETs can be formed on bulk wafer substrates or on SOI (silicon-on-insulator) substrates. In bulk wafers, isolation is formed with implanted wells and shallow trench isolation (STI) oxide separating one fin from another. In SOI, the fins are formed in the silicon layer, and no wells are needed because of the isolating dielectric that is already present in the SOI wafer.